Vrudhula, V. M.: search on Z-Library

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1

[ACM Press the 2017 ACM/SIGDA International Symposium - Monterey, California, USA (2017.02.22-2017.02.24)] Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '17 - Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Year:

2017

Language:

english

File:

PDF, 517 KB

english, 2017

2

[ACM Press the 2016 ACM/SIGDA International Symposium - Monterey, California, USA (2016.02.21-2016.02.23)] Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '16 - Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

Suda, Naveen, Chandra, Vikas, Dasika, Ganesh, Mohanty, Abinash, Ma, Yufei, Vrudhula, Sarma, Seo, Jae-sun, Cao, Yu

Year:

2016

Language:

english

File:

PDF, 607 KB

english, 2016

3

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 3.94 MB

english, 2018

4

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Kulkarni, Niranjan, Yang, Jinghua, Seo, Jae-Sun, Vrudhula, Sarma

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2016

Language:

english

File:

PDF, 3.21 MB

english, 2016

5

[IEEE 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Lisbon, Portugal (2015.5.24-2015.5.27)] 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Fast and robust differential flipflops and their extension to multi-input threshold gates

Yang, Jinghua, Kulkarni, Niranjan, Davis, Joseph, Vrudhula, Sarma

Year:

2015

Language:

english

File:

PDF, 447 KB

english, 2015

6

[IEEE 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Baltimore, MD, USA (2017.5.28-2017.5.31)] 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - End-to-end scalable FPGA accelerator for deep residual networks

Ma, Yufei, Kim, Minkyu, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Year:

2017

Language:

english

File:

PDF, 255 KB

english, 2017

7

[IEEE 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Paris, France (2014.7.8-2014.7.10)] 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

Yang, Jinghua, Kulkarni, Niranjan, Yu, Shimeng, Vrudhula, Sarma

Year:

2014

Language:

english

File:

PDF, 262 KB

english, 2014

8

Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations

Bhardwaj, S., Vrudhula, S.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2008

Language:

english

File:

PDF, 614 KB

english, 2008

9

[ACM Press the conference - Munich, Germany (2008.03.10-2008.03.14)] Proceedings of the conference on Design, automation and test in Europe - DATE '08 - Current source based standard cell model for accurate signal integrity and timing analysis

Goel, Amit, Vrudhula, Sarma

Year:

2008

Language:

english

File:

PDF, 920 KB

english, 2008

10

[IEEE 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Lisbon, Portugal (2015.5.24-2015.5.27)] 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Design of threshold logic gates using emerging devices

Vrudhula, Sarma, Kulkami, Niranjan, Yang, Jinghua

Year:

2015

Language:

english

File:

PDF, 773 KB

english, 2015

11

Analysis of Power Supply Noise in the Presence of Process Variations

Ghanta, P., Vrudhula, S.

Journal:

IEEE Design & Test of Computers

Year:

2007

Language:

english

File:

PDF, 512 KB

english, 2007

12

Evaluation of Automated ECG Monitoring: Theoretical Model Based upon Point Process Techniques

L.Julian Haywood, Vrudhula K. Murthy, George A. Harvey

Journal:

Applied Mathematics and Computation

Year:

1977

Language:

english

File:

PDF, 371 KB

english, 1977

13

[IEEE 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) - Seattle, WA, USA (2020.6.14-2020.6.19)] 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) - Enabling Incremental Knowledge Transfer for Object Detection at the Edge

Farhadi, Mohammad, Ghasemi, Mehdi, Vrudhula, Sarma, Yang, Yezhou

Year:

2020

File:

PDF, 1.16 MB

2020

14

Techniques for estimating test length under random test

Amitava Majumdar, Sarma B. K. Vrudhula

Journal:

Journal of Electronic Testing

Year:

1994

Language:

english

File:

PDF, 1.13 MB

english, 1994

15

[IEEE 2015 IEEE Custom Integrated Circuits Conference - CICC 2015 - San Jose, CA, USA (2015.9.28-2015.9.30)] 2015 IEEE Custom Integrated Circuits Conference (CICC) - Dynamic and leakage power reduction of ASICs using configurable threshold logic gates

Yang, Jinghua, Davis, Joseph, Kulkarni, Niranjan, Seo, Jae-sun, Vrudhula, Sarma

Year:

2015

Language:

english

File:

PDF, 557 KB

english, 2015

16

[IEEE 2016 26th International Conference on Field Programmable Logic and Applications (FPL) - Lausanne, Switzerland (2016.8.29-2016.9.2)] 2016 26th International Conference on Field Programmable Logic and Applications (FPL) - Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Yufei Ma,, Suda, Naveen, Yu Cao,, Seo, Jae-sun, Vrudhula, Sarma

Year:

2016

Language:

english

File:

PDF, 362 KB

english, 2016

17

[IEEE 2016 IEEE International Symposium on Circuits and Systems (ISCAS) - Montréal, QC, Canada (2016.5.22-2016.5.25)] 2016 IEEE International Symposium on Circuits and Systems (ISCAS) - Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons

Mahalanabis, D., Sivaraj, M., Chen, W., Shah, S., Barnaby, H. J., Kozicki, M. N., Christen, J. Blain, Vrudhula, S.

Year:

2016

Language:

english

File:

PDF, 1.09 MB

english, 2016

18

Adaptive multiuser online reconfigurable engine

Rakhmatov, D.N., Vrudhula, S.B.K., Brown, T.J., Nagarandal, A.

Journal:

IEEE Design & Test of Computers

Year:

2000

Language:

english

File:

PDF, 1.02 MB

english, 2000

19

[IEEE IEEE Custom Integrated Circuits Conference 2006 - San Jose, CA, USA (2006.09.10-2006.09.13)] IEEE Custom Integrated Circuits Conference 2006 - Predictive Modeling of the NBTI Effect for Reliable Design

Bhardwaj, Sarvesh, Wang, Wenping, Vattikonda, Rakesh, Cao, Yu, Vrudhula, Sarma

Year:

2006

Language:

english

File:

PDF, 2.67 MB

english, 2006

20

[IEEE 2010 International Conference on Microelectronics (ICM) - Cairo, Egypt (2010.12.19-2010.12.22)] 2010 International Conference on Microelectronics - Design of a robust, high performance standard cell threshold logic family for DSM technology

Leshner, Samuel, Kulkarni, Niranjan, Vrudhula, Sarma, Berezowski, Krzysztof

Year:

2010

Language:

english

File:

PDF, 205 KB

english, 2010

21

[IEEE Conference Publications Design, Automation and Test in Europe - Grenoble, France (2015.03.9-2015.03.13)] Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 - Technology-design Co-optimization of Resistive Cross-point Array for Accelerating Learning Algorithms on Chip

Chen, Pai-Yu, Kadetotad, Deepak, Xu, Zihan, Mohanty, Abinash, Lin, Binbin, Ye, Jieping, Vrudhula, Sarma, Seo, Jae-sun, Cao, Yu, Yu, Shimeng

Year:

2015

Language:

english

File:

PDF, 1.81 MB

english, 2015

22

[IEEE Comput. Soc 8th IEEE International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype - Chapel Hill, NC, USA (24-26 June 1997)] Proceedings 8th IEEE International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype - Macro-instruction generation for dynamic logic caching

McCarley, K., Vrudhula, S.B.K.

Year:

1997

Language:

english

File:

PDF, 664 KB

english, 1997

23

[IEEE 2019 IEEE 37th International Conference on Computer Design (ICCD) - Abu Dhabi, United Arab Emirates (2019.11.17-2019.11.20)] 2019 IEEE 37th International Conference on Computer Design (ICCD) - Threshold Logic in a Flash

Wagle, Ankit, Singh, Gian, Yang, Jinghua, Khatri, Sunil, Vrudhula, Sarma

Year:

2019

File:

PDF, 1.06 MB

2019

24

Performance Modeling for CNN Inference Accelerators on FPGA

Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2019

Language:

english

File:

PDF, 6 KB

english, 2019

25

Thermal aware floorplanning incorporating temperature dependent wire delay estimation

Winther, Andreas Thor, Liu, Wei, Nannarelli, Alberto, Vrudhula, Sarma

Journal:

Microprocessors and Microsystems

Year:

2015

Language:

english

File:

PDF, 761 KB

english, 2015

26

Representation of the interevent intervals between a set of nonuniformly distributed “points” or “events”*

John Richardson, Vrudhula K. Murthy, L.Julian Haywood

Journal:

Applied Mathematics and Computation

Year:

1977

Language:

english

File:

PDF, 235 KB

english, 1977

27

Scalable model for predicting the effect of negative bias temperature instability for reliable design

Bhardwaj, S., Wang, W., Vattikonda, R., Cao, Y., Vrudhula, S.

Journal:

IET Circuits Devices & Systems

Year:

2008

Language:

english

File:

PDF, 551 KB

english, 2008

28

Sample size determination for comparing two therapies taking both the α (type I or false positive) error and the β (type II or false negative) error into consideration

Vrudhula K. Murthy, L.Julian Haywood

Journal:

Applied Mathematics and Computation

Year:

1977

Language:

english

File:

PDF, 291 KB

english, 1977

29

A Strategy to Minimize Reactive Metabolite Formation: Discovery of ( S )-4-(1-Cyclopropyl-2-methoxyethyl)-6-[6-(difluoromethoxy)-2,5-dimethylpyridin-3-ylamino]-5-oxo-4,5-dihydropyrazine-2-carbonitrile as a Potent, Orally Bioavailable Corticotropin-Releasing Factor-1 Receptor Antagonist †

Hartz, Richard A., Ahuja, Vijay T., Zhuo, Xiaoliang, Mattson, Ronald J., Denhart, Derek J., Deskus, Jeffrey A., Vrudhula, Vivekananda M., Pan, Senliang, Ditta, Jonathan L., Shu, Yue-Zhong, Grace, Jame

Journal:

Journal of Medicinal Chemistry

Year:

2009

Language:

english

File:

PDF, 1.16 MB

english, 2009

30

[IEEE Comput. Soc IEEE International Symposium on Parallel and Distributed Processing - San Francisco, CA, USA (23-27 April 2001)] Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001 - Minimizing routing configuration cost in dynamically reconfigurable FPGAs

Rakhmatov, D., Vrudhula, S.B.K.

Year:

2001

Language:

english

File:

PDF, 159 KB

english, 2001

31

Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors

Hanumaiah, V., Vrudhula, S., Chatha, K.S.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2011

Language:

english

File:

PDF, 1.05 MB

english, 2011

32

Construction, Expression, and Activities of L49-sFv-β-Lactamase, a Single-Chain Antibody Fusion Protein for Anticancer Prodrug Activation

Siemers, Nathan O., Kerr, David E., Yarnold, Susan, Stebbins, Mark R., Vrudhula, Vivekananda M., Hellström, Ingegerd, Hellström, Karl Erik, Senter, Peter D.

Journal:

Bioconjugate Chemistry

Year:

1997

Language:

english

File:

PDF, 298 KB

english, 1997

33

Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors

Hanumaiah, Vinay, Vrudhula, Sarma

Journal:

IEEE Transactions on Computers

Year:

2012

Language:

english

File:

PDF, 1.89 MB

english, 2012

34

[IEEE ICCAD 2004. International Conference on Computer Aided Design - San Jose, CA, USA (7-11 Nov. 2004)] IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. - Energy optimization for a two-device data flow chain

Rao, R., Vrudhula, S.

Year:

2004

Language:

english

File:

PDF, 564 KB

english, 2004

35

[IEEE 2003. Design Automation Conference - Anaheim, CA, USA (2-6 June 2003)] Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) - Computation and refinement of statistical bounds on circuit delay

Agarwal, A., Blaauw, D., Zolotov, V., Vrudhula, S.

Year:

2003

Language:

english

File:

PDF, 771 KB

english, 2003

36

[IEEE 34th Design Automation Conference - Anaheim CA (June 9-13, 1997)] Proceedings of the 34th Design Automation Conference - An Investigation Of Power Delay Trade-offs On Powerpc

Qi Wang,, Vrudhula, S.B.K., Ganguly, S.

Year:

1997

Language:

english

File:

PDF, 500 KB

english, 1997

37

[IEEE Design, Automation and Test in Europe - Munich, Germany (07-11 March 2005)] Design, Automation and Test in Europe - Stochastic Power Grid Analysis Considering Process Variations

Ghanta, P., Vrudhula, S., Panda, R., Wang, J.

Year:

2005

Language:

english

File:

PDF, 150 KB

english, 2005

38

[ACM Press the 2001 international symposium - Huntington Beach, California, United States (2001..-..)] Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01 - Time-to-failure estimation for batteries in portable electronic systems

Rakhamtov, Daler, Vrudhula, Sarma

Year:

2001

Language:

english

File:

PDF, 218 KB

english, 2001

39

[ACM Press the 8th ACM/IEEE international workshop - Monterey, California, USA (2002.12.02-2002.12.03)] Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02 - Statistical timing analysis using bounds and selective enumeration

Agarwal, Aseem, Blaauw, David, Zolotov, Vladimir, Vrudhula, Sarma

Year:

2002

Language:

english

File:

PDF, 266 KB

english, 2002

40

[ACM Press the 54th Annual Design Automation Conference 2017 - Austin, TX, USA (2017.06.18-2017.06.22)] Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17 - A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits

Kulkarni, Niranjan, Dengi, Aykut, Vrudhula, Sarma

Year:

2017

Language:

english

File:

PDF, 571 KB

english, 2017

41

Design, synthesis and evaluation of constrained tetrahydroimidazopyrimidine derivatives as antagonists of corticotropin-releasing factor type 1 receptor (CRF1R)

Vivekananda M. Vrudhula, Bireshwar Dasgupta, Sokhom S. Pin, Kevin D. Burris, Lynn A. Balanda, Lawrence K. Fung, Tracey Fiedler, Kaitlin E. Browman, Matthew T. Taber, Jie Zhang, John E. Macor, Gene M.

Journal:

Bioorganic & Medicinal Chemistry Letters

Year:

2010

Language:

english

File:

PDF, 2.09 MB

english, 2010

42

Analogs of a potent maxi-K potassium channel opener with an improved inhibitory profile toward cytochrome P450 isozymes

Vivekananda M. Vrudhula, Bireshwar Dasgupta, Christopher G. Boissard, Valentin K. Gribkoff, Kenneth S. Santone, Richard A. Dalterio, Nicholas J. Lodge, John E. Starrett Jr.

Journal:

Bioorganic & Medicinal Chemistry Letters

Year:

2005

Language:

english

File:

PDF, 187 KB

english, 2005

43

Chiral separation of potent corticotropin-releasing factor-1 receptor antagonists by supercritical fluid chromatography

Jingfang Qian-Cutrone, Richard Hartz, Vijay T. Ahuja, Vivekananda M. Vrudhula, Dauh-Rurng Wu, Richard A. Dalterio, David Wang-Iverson, Joanne J. Bronson

Journal:

Journal of Pharmaceutical and Biomedical Analysis

Year:

2011

Language:

english

File:

PDF, 193 KB

english, 2011

44

Analysis of power spectral densities of electrocardiograms

Vrudhula K. Murthy, L. Julian Haywood, John Richardson, Robert Kalaba, Steven Salzberg, George Harvey, David Vereeke

Journal:

Mathematical Biosciences

Year:

1971

Language:

english

File:

PDF, 469 KB

english, 1971

45

A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations

Bhardwaj, S., Vrudhula, S., Goel, A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2008

Language:

english

File:

PDF, 951 KB

english, 2008

46

Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors

Shrivastava, A., Kannan, D., Bhardwaj, S., Vrudhula, S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2010

Language:

english

File:

PDF, 2.10 MB

english, 2010

47

Trichoverritone and 16-hydroxyroridin L-2, new trichothecenes from myrothecium roridum

Bruce B. Jarvis, Vivekananda M. Vrudhula, Gowsala Pavanasasivam

Journal:

Tetrahedron Letters

Year:

1983

Language:

english

File:

PDF, 251 KB

english, 1983

48

Spintronic Threshold Logic Array (STLA)—A compact, low leakage, non-volatile gate array architecture

Nukala, Nishant S., Kulkarni, Niranjan, Vrudhula, Sarma

Journal:

Journal of Parallel and Distributed Computing

Year:

2014

Language:

english

File:

PDF, 1.11 MB

english, 2014

49

Synthesis and binding studies of crown ethers bearing pharmacophoric groups: epoxy lariat crown ethers

Jarvis, Bruce B., Vrudhula, Vivekananda M., Dishong, Dennis M., Gokel, George W.

Journal:

Journal of Organic Chemistry

Year:

1984

Language:

english

File:

PDF, 693 KB

english, 1984

50

[IEEE 7th International Symposium on Quality Electronic Design (ISQED'06) - San Jose, CA, USA (27-29 March 2006)] 7th International Symposium on Quality Electronic Design (ISQED'06) - Variational Interconnect Delay Metrics for Statistical Timing Analysis

Ghanta, P., Vrudhula, S.

Year:

2006

Language:

english

File:

PDF, 230 KB

english, 2006

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